A semiconductor device having a three-dimensional structure has attracted interest as an effective structure which avoids various obstacles with which a semiconductor device having a two-dimensional structure confronts, such as limits of lithography techniques, tendency of the operation speed to be saturated by increase in wiring resistance and parasitic effects, and high electrical field effects by miniaturization in element dimensions, and keeps improving the integration level, by integrating three-dimensionally semiconductor elements in a stacked multi-layer structure, by stacking semiconductor active layers.
Semiconductor devices having three-dimensional structures are described, for example, in Japanese Patent Application Laid-Open Publication No. H11-261000 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 2002-334967 (Patent Document 2), and also methods of manufacturing semiconductor devices having three-dimensional structures by mutually attaching semiconductor substrates in which semiconductor elements are formed are disclosed. These documents also disclose structures in which through-electrodes called vertical mutual connection bodies or embedded connection electrodes are formed in grooves penetrating from the main surfaces to the rear surfaces of desired semiconductor substrates so that the main surfaces and the rear surfaces of the semiconductor substrates are electrically conductive each other.
FIG. 15 of “Denso Technical Review Vol. 6 No. 2 2001” (Non-Patent Document 1) discloses techniques of embedding copper (Cu) in connection holes of a semiconductor device having a three-dimensional structure by a plating method.    Patent Document 1: Japanese Patent Application Laid-Open Publication No. H11-261000    Patent Document 2: Japanese Patent Application Laid-Open Publication No. 2002-334967    Non-Patent Document: “Denso Technical Review Vol. 6 No. 2 2001” (FIG. 15)